SDRAM Controller Core n2cpu_nii51005

© March 2009 Altera Corporation 1. SDRAM Controller Core Quartus II Handbook Version 9.0 Volume 5: Embedded Peripherals Core Overview The SDRAM controller core with Avalon® interface provides an Avalon Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM controller allows designers to create custom systems in an Altera® device that connect easily to SDRAM chips. The SDRAM controller supports standard SDRAM as described in the PC100 specification. SDRAM is commonly used in cost-sensitive applications requiring large amounts of volatile memory. While SDRAM is relatively inexpensive, control logic is required to perform refresh operations, open-row management, and other delays and command sequences. The SDRAM controller connects to one or more SDRAM chips, and handles all SDRAM protocol requirements. Internal to the device, the core presents an Avalon-MM slave port that appears as linear memory (flat address space) to Avalon-MM master peripherals. The core can access SDRAM subsystems with various data widths (8, 16, 32, or 64 bits), various memory sizes, and multiple chip selects. The Avalon-MM interface is latency-aware, allowing read transfers to be pipelined. The core can optionally share its address and data buses with other off-chip Avalon-MM tri-state devices. This feature is valuable in systems that have limited I/O pins, yet must connect to multiple memory chips in addition to SDRAM. The SDRAM controller core with Avalon interface is SOPC Builder-ready and integrates easily into any SOPC Builder-generated system. This chapter contains the following sections: ■ “Functional Description” on page 1–2 ■ “Device Support” on page 1–5 ■ “Instantiating the Core in SOPC Builder” on page 1–5 ■ “Hardware Simulation Considerations” on page 1–7 ■ “Software Programming Model” on page 1–10 ■ “Clock, PLL and Timing Considerations” on page 1–10 NII51005-9.0.0 1–2 Chapter 1: SDRAM Controller Core Functional Description Functional Description Figure 1–1 shows a block diagram of the SDRAM controller core connected to an external SDRAM chip. The following sections describe the components of the SDRAM controller core in detail. All options are specified at system generation time, and cannot be changed at runtime. Avalon-MM Interface The Avalon-MM slave port is the user-visible part of the SDRAM controller core. The slave port presents a flat, contiguous memory space as large as the SDRAM chip(s). When accessing the slave port, the details of the PC100 SDRAM protocol are entirely transparent. The Avalon-MM interface behaves as a simple memory interface. There are no memory-mapped configuration registers. The Avalon-MM slave port supports peripheral-controlled wait states for read and write transfers. The slave port stalls the transfer until it can present valid data. The slave port also supports read transfers with variable latency, enabling high-bandwidth, pipelined read transfers. When a master peripheral reads sequential addresses from the slave port, the first data returns after an initial period of latency. Subsequent reads can produce new data every clock cycle. However, data is not guaranteed to return every clock cycle, because the SDRAM controller must pause periodically to refresh the SDRAM. f For details about Avalon-MM transfer types, refer to the Avalon Interface Specifications. Figure 1–1. SDRAM Controller with Avalon Interface Block Diagram Avalon-MM slave interface to on-chip logic SDRAM Controller Core data, control Av al on -M M S la ve P or t clock waitrequest readdatavalid dq dqm PLL Phase Shift In te rfa ce to S DR AM p in s Altera FPGA clk addr ras cas cs cke ba we Control Logic address SDRAM Clock Controller Clock Clock Source SDRAM Chip (PC100) Quartus II Handbook Version 9.0 Volume 5: Embedded Peripherals © March 2009 Altera Corporation Chapter 1: SDRAM Controller Core 1–3 Functional Description Off-Chip SDRAM Interface The interface to the external SDRAM chip presents the signals defined by the PC100 standard. These signals must be connected externally to the SDRAM chip(s) through I/O pins on the Altera device. Signal Timing and Electrical Characteristics The timing and sequencing of signals depends on the configuration of the core. The hardware designer configures the core to match the SDRAM chip chosen for the system. See “Instantiating the Core in SOPC Builder” on page 1–5 for details. The electrical characteristics of the device pins depend on both the target device family and the assignments made in the Quartus® II software. Some device families support a wider range of electrical standards, and therefore are capable of interfacing with a greater variety of SDRAM chips. For details, refer to the device handbook for the target device family. Synchronizing Clock and Data Signals The clock for the SDRAM chip (SDRAM clock) must be driven at the same frequency as the clock for the Avalon-MM interface on the SDRAM controller (controller clock). As in all synchronous designs, you must ensure that address, data, and control signals at the SDRAM pins are stable when a clock edge arrives. As shown in Figure 1–1, you can use an on-chip phase-locked loop (PLL) to alleviate clock skew between the SDRAM controller core and the SDRAM chip. At lower clock speeds, the PLL might not be necessary. At higher clock rates, a PLL is necessary to ensure that the SDRAM clock toggles only when signals are stable on the pins. The PLL block is not part of the SDRAM controller core. If a PLL is necessary, you must instantiate it manually. You can instantiate the PLL core interface, which is an SOPC Builder component, or instantiate an ALTPLL megafunction outside the SOPC Builder system module. If you use a PLL, you must tune the PLL to introduce a clock phase shift so that SDRAM clock edges arrive after synchronous signals have stabilized. See “Clock, PLL and Timing Considerations” on page 1–10 for details. f For more information about instantiating a PLL in your SOPC Builder system, refer to PLL Core chapter in volume 5 of the Quartus II Handbook. The Nios® II development tools provide example hardware designs that use the SDRAM controller core in conjunction with a PLL, which you can use as a reference for your custom designs. The Nios II development tools are available free for download from www.altera.com. Clock Enable (CKE) Not Supported The SDRAM controller does not support clock-disable modes. The SDRAM controller permanently asserts the CKE signal on the SDRAM. Sharing Pins with Other Avalon-MM Tri-State Devices If an Avalon-MM tri-state bridge is present in the SOPC Builder system, the SDRAM controller core can share pins with the existing tri-state bridge. In this case, the core’s addr, dq (data) and dqm (byte-enable) pins are shared with other devices connected to the Avalon-MM tri-state bridge. This feature conserves I/O pins, which is valuable in systems that have multiple external memory chips (for example, flash, SRAM, and SDRAM), but too few pins to dedicate to the SDRAM chip. See “Performance Considerations” for details about how pin sharing affects performance. © March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 5: Embedded Peripherals 1–4 Chapter 1: SDRAM Controller Core Functional Description 1 The SDRAM addresses must connect all address bits regardless of the size of the word so that the low-order address bits on the tri-state bridge align with the low-order address bits on the memory device. The Avalon-MM tristate address signal always presents a byte address. It is not possible to drop A0 of the tri-state bridge for memories when the smallest access size is 16 bits or A0-A1 of the tri-state bridge when the smallest access size is 32 bits. Board Layout and Pinout Considerations When making decisions about the board layout and device pinout, try to minimize the skew between the SDRAM signals. For example, when assigning the device pinout, group the SDRAM signals, including the SDRAM clock output, physically close together. Also, you can use the Fast Input Register and Fast Output Register logic options in the Quartus II software. These logic options place registers for the SDRAM signals in the I/O cells. Signals driven from registers in I/O cells have similar timing characteristics, such as tCO, tSU, and tH. Performance Considerations Under optimal conditions, the SDRAM controller core’s bandwidth approaches one word per clock cycle. However, because of the overhead associated with refreshing the SDRAM, it is impossible to reach one word per clock cycle. Other factors affect the core’s performance, as described in the following sections. Open Row Management SDRAM chips are arranged as multiple banks of memory, in which each bank is capable of independent open-row address management. The SDRAM controller core takes advantage of open-row management for a single bank. Continuous reads or writes within the same row and bank operate at rates approaching one word per clock. Applications that frequently access different destination banks require extra management cycles to open and close rows. Sharing Data and Address Pins When the controller shares pins with other tri-state devices, average access time usually increases and bandwidth decreases. When access to the tri-state bridge is granted to other devices, the SDRAM incurs overhead to open and close rows. Furthermore, the SDRAM controller has to wait several clock cycles before it is granted access again. To maximize bandwidth, the SDRAM controller automatically maintains control of the tri-state bridge as long as back-to-back read or write transactions continue within the same row and bank. 1 This behavior may degrade the average access time for other devices sharing the Avalon-MM tri-state bridge. The SDRAM controller closes an open row whenever there is a break in back-to-back transactions, or whenever a refresh transaction is required. As a result: ■ The controller cannot permanently block access to other devices sharing the tri-state bridge. Quartus II Handbook Version 9.0 Volume 5: Embedded Peripherals © March 2009 Altera Corporation Chapter 1: SDRAM Controller Core 1–5 Device Support ■ The controller is guaranteed not to violate the SDRAM’s row open time limit. Hardware Design and Target Device The target device affects the maximum achievable clock frequency of a hardware design. Certain device families achieve higher fMAX performance than other families. Furthermore, within a device family, faster speed grades achieve higher performance. The SDRAM controller core can achieve 100 MHz in Altera’s high-performance device families, such as Stratix® series. However, the core might not achieve 100 MHz performance in all Altera device families. The fMAX performance also depends on the SOPC Builder system design. The SDRAM controller clock can also drive other logic in the system module, which might affect the maximum achievable frequency. For the SDRAM controller core to achieve fMAX performance of 100 MHz, all components driven by the same clock must be designed for a 100 MHz clock rate, and timing analysis in the Quartus II software must verify that the overall hardware design is capable of 100 MHz operation. Device Support The SDRAM Controller with Avalon interface core supports all Altera device families. Different device families support different I/O standards, which may affect the ability of the core to interface to certain SDRAM chips. For details about supported I/O types, refer to the device handbook for the target device family. Instantiating the Core in SOPC Builder Use the MegaWizard™ interface for the SDRAM controller in SOPC Builder to specify hardware and simulation features. The SDRAM controller MegaWizard has two pages: Memory Profile and Timing. This section describes the options available on each page. The Presets list offers several pre-defined SDRAM configurations as a convenience. If the SDRAM subsystem on the target board matches one of the preset configurations, you can configure the SDRAM controller core easily by selecting the appropriate preset value. The following preset configurations are defined: ■ Micron MT8LSDT1664HG module ■ Four SDR100 8 MByte × 16 chips ■ Single Micron MT48LC2M32B2-7 chip ■ Single Micron MT48LC4M32B2-7 chip ■ Single NEC D4564163-A80 chip (64 MByte × 16) ■ Single Alliance AS4LC1M16S1-10 chip ■ Single Alliance AS4LC2M8S0-10 chip Selecting a preset configuration automatically changes values on the Memory Profile and Timing tabs to match the specific configuration. Altering a configuration setting on any page changes the Preset value to custom. © March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 5: Embedded Peripherals 1–6 Chapter 1: SDRAM Controller Core Instantiating the Core in SOPC Builder Memory Profile Page The Memory Profile page allows you to specify the structure of the SDRAM subsystem such as address and data bus widths, the number of chip select signals, and the number of banks. Table 1–1 lists the settings available on the Memory Profile page. Based on the settings entered on the Memory Profile page, the wizard displays the expected memory capacity of the SDRAM subsystem in units of megabytes, megabits, and number of addressable words. Compare these expected values to the actual size of the chosen SDRAM to verify that the settings are correct. Table 1–1. Memory Profile Page Settings Settings Allowed Values Default Values Description Data Width 8, 16, 32, 64 32 SDRAM data bus width. This value determines the width of the dq bus (data) and the dqm bus (byte-enable). Architecture Settings Chip Selects 1, 2, 4, 8 1 Number of independent chip selects in the SDRAM subsystem. By using multiple chip selects, the SDRAM controller can combine multiple SDRAM chips into one memory subsystem. Banks 2, 4 4 Number of SDRAM banks. This value determines the width of the ba bus (bank address) that connects to the SDRAM. The correct value is provided in the data sheet for the target SDRAM. Address Width Settings Row 11, 12, 13, 14 12 Number of row address bits. This value determines the width of the addr bus. The Row and Column values depend on the geometry of the chosen SDRAM. For example, an SDRAM organized as 4096 (212) rows by 512 columns has a Row value of 12. Column >= 8, and less than Row value 8 Number of column address bits. For example, the SDRAM organized as 4096 rows by 512 (29) columns has a Column value of 9. Share pins via tri-state bridge dq/dqm/addr I/O pins On, Off Off When set to No, all pins are dedicated to the SDRAM chip. When set to Yes, the addr, dq, and dqm pins can be shared with a tristate bridge in the system. In this case, select the appropriate tristate bridge from the pull-down menu. Include a functional memory model in the system testbench On, Off On When on, SOPC Builder creates a functional simulation model for the SDRAM chip. This default memory model accelerates the process of creating and verifying systems that use the SDRAM controller. See “Hardware Simulation Considerations” on page 1–7. Quartus II Handbook Version 9.0 Volume 5: Embedded Peripherals © March 2009 Altera Corporation Chapter 1: SDRAM Controller Core 1–7 Hardware Simulation Considerations Timing Page The Timing page allows designers to enter the timing specifications of the SDRAM chip(s) used. The correct values are available in the manufacturer’s data sheet for the target SDRAM. Table 1–2 lists the settings available on the Timing page. Regardless of the exact timing values you specify, the actual timing achieved for each parameter is an integer multiple of the Avalon clock period. For the Issue one refresh command every parameter, the actual timing is the greatest number of clock cycles that does not exceed the target value. For all other parameters, the actual timing is the smallest number of clock ticks that provides a value greater than or equal to the target value. Hardware Simulation Considerations This section discusses considerations for simulating systems with SDRAM. Three major components are required for simulation: ■ A simulation model for the SDRAM controller. ■ A simulation model for the SDRAM chip(s), also called the memory model. ■ A simulation testbench that wires the memory model to the SDRAM controller pins. Some or all of these components are generated by SOPC Builder at system generation time. Table 1–2. Timing Page Settings Settings Allowed Values Default Value Description CAS latency 1, 2, 3 3 Latency (in clock cycles) from a read command to data out. Initialization refresh cycles 1–8 2 This value specifies how many refresh cycles the SDRAM controller performs as part of the initialization sequence after reset. Issue one refresh command every — 15.625 µs This value specifies how often the SDRAM controller refreshes the SDRAM. A typical SDRAM requires 4,096 refresh commands every 64 ms, which can be achieved by issuing one refresh command every 64 ms / 4,096 = 15.625 μs. Delay after power up, before initialization — 100 µs The delay from stable clock and power to SDRAM initialization. Duration of refresh command (t_rfc) — 70 ns Auto Refresh period. Duration of precharge command (t_rp) — 20 ns Precharge command period. ACTIVE to READ or WRITE delay (t_rcd) — 20 ns ACTIVE to READ or WRITE delay. Access time (t_ac) — 17 ns Access time from clock edge. This value may depend on CAS latency. Write recovery time (t_wr, No auto precharge) — 14 ns Write recovery if explicit precharge commands are issued. This SDRAM controller always issues explicit precharge commands. © March 2009 Altera Corporation Quartus II Handbook Version 9.0 Volume 5: Embedded Peripherals 1–8 Chapter 1: SDRAM Controller Core Example Configurations SDRAM Controller Simulation Model The SDRAM controller design files generated by SOPC Builder are suitable for both synthesis and simulation. Some simulation features are implemented in the HDL using “translate on/off” synthesis directives that make certain sections of HDL code invisible to the synthesis tool. The simulation features are implemented primarily for easy simulation of Nios and Nios II processor systems using the ModelSim® simulator. The SDRAM controller simulation model is not ModelSim specific. However, minor changes may be required to make the model work with other simulators. c If you change the simulation directives to create a custom simulation flow, be aware that SOPC Builder overwrites existing files during system generation. Take precautions to ensure your changes are not overwritten. f Refer to AN 351: Simulating Nios II Processor Designs for a demonstration of simulation of the SDRAM controller in the context of Nios II embedded processor systems. SDRAM Memory Model This section describes the two options for simulating a memory model of the SDRAM chip(s). Using the Generic Memory Model If the Include a functional memory model the system testbench option is enabled at system generation, SOPC Builder generates an HDL simulation model for the SDRAM memory. In the auto-generated system testbench, SOPC Builder automatically wires this memory model to the SDRAM controller pins. Using the automatic memory model and testbench accelerates the process of creating and verifying systems that use the SDRAM controller. However, the memory model is a generic functional model that does not reflect the true timing or functionality of real SDRAM chips. The generic model is always structured as a single, monolithic block of memory. For example, even for a system that combines two SDRAM chips, the generic memory model is implemented as a single entity. Using the SDRAM Manufactu