74HC00与非门

DATA SHEET Product specification Supersedes data of 1997 Aug 26 2003 Jun 30 INTEGRATED CIRCUITS 74HC00; 74HCT00 Quad 2-input NAND gate 2003 Jun 30 2 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC00/74HCT00 provide the 2-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC00 the condition is VI = GND to VCC. For 74HCT00 the condition is VI = GND to VCC − 1.5 V. FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; L = LOW voltage level. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 74HC00 74HCT00 tPHL/tPLH propagation delay nA, nB to nY CL = 15 pF; VCC = 5 V 7 10 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per gate notes 1 and 2 22 22 pF INPUT OUTPUT nA nB nY L L H L H H H L H H H L 2003 Jun 30 3 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 ORDERING INFORMATION TYPE NUMBER PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC00N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HCT00N −40 to +125 °C 14 DIP14 plastic SOT27-1 74HC00D −40 to +125 °C 14 SO14 plastic SOT108-1 74HCT00D −40 to +125 °C 14 SO14 plastic SOT108-1 74HC00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1 74HCT00DB −40 to +125 °C 14 SSOP14 plastic SOT337-1 74HC00PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1 74HCT00PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1 74HC00BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1 74HCT00BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 1B data input 3 1Y data output 4 2A data input 5 2B data input 6 2Y data output 7 GND ground (0 V) 8 3Y data output 9 3A data input 10 3B data input 11 4Y data output 12 4A data input 13 4B data input 14 VCC supply voltage Fig.1 Pin configuration DIP14, SO14 and (T)SSOP14. handbook, halfpage 00 MNA210 1 2 3 4 5 6 7 1A 1B 1Y 2A 2B 2Y GND VCC 4B 4A 4Y 3B 3A 3Y 14 13 12 11 10 9 8 2003 Jun 30 4 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 Fig.2 Pin configuration DHVQFN14. handbook, halfpage 1 14 1A VCC 7 2 3 4 5 6 1B 1Y 2A 2B 2Y 13 12 11 10 9 4B 4A 4Y 3B 3A 8 GND 3Y MNA950 GND(1) Top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. handbook, halfpage MNA211 A B Y Fig.3 Logic diagram (one gate). handbook, halfpage MNA212 1Y1A 3 1B 1 2 2Y2A 6 2B 4 5 3Y3A 8 3B 9 10 4Y4A 11 4B 12 13 Fig.4 Function diagram. handbook, halfpage MNA246 3& & & & 2 1 6 5 4 8 10 9 11 13 12 Fig.5 IEC logic symbol. 2003 Jun 30 5 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 RECOMMENDED OPERATING CONDITIONS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). Note 1. For DIP14 packages: above 70 °C derate linearly with 12 mW/K. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature see DC and AC characteristics per device −40 +25 +125 −40 +25 +125 °C tr, tf input rise and fall times VCC = 2.0 V − − 1000 − − − ns VCC = 4.5 V − 6.0 500 − 6.0 500 ns VCC = 6.0 V − − 400 − − − ns SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +7.0 V IIK input diode current VI < −0.5 V or VI > VCC + 0.5 V − ±20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC, IGND VCC or GND current − ±50 mA Tstg storage temperature −65 +150 °C Ptot power dissipation Tamb = −40 to +125 °C; note 1 − 500 mW 2003 Jun 30 6 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DC CHARACTERISTICS Type 74HC00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 2.0 1.5 1.2 − V 4.5 3.15 2.4 − V 6.0 4.2 3.2 − V VIL LOW-level input voltage 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA 2.0 1.9 2.0 − V IO = −20 µA 4.5 4.4 4.5 − V IO = −20 µA 6.0 5.9 6.0 − V IO = −4.0 mA 4.5 3.84 4.32 − V IO = −5.2 mA 6.0 5.34 5.81 − V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA 2.0 − 0 0.1 V IO = 20 µA 4.5 − 0 0.1 V IO = 20 µA 6.0 − 0 0.1 V IO = 4.0 mA 4.5 − 0.15 0.33 V IO = 5.2 mA 6.0 − 0.16 0.33 V ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 6.0 − − ±.5.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 20 µA 2003 Jun 30 7 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 Note 1. All typical values are measured at Tamb = 25 °C. Tamb = −40 to +125 °C VIH HIGH-level input voltage 2.0 1.5 − − V 4.5 3.15 − − V 6.0 4.2 − − V VIL LOW-level input voltage 2.0 − − 0.5 V 4.5 − − 1.35 V 6.0 − − 1.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA 2.0 1.9 − − V IO = −20 µA 4.5 4.4 − − V IO = −20 µA 6.0 5.9 − − V IO = −4.0 mA 4.5 3.7 − − V IO = −5.2 mA 6.0 5.2 − − V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA 2.0 − − 0.1 V IO = 20 µA 4.5 − − 0.1 V IO = 20 µA 6.0 − − 0.1 V IO = 4.0 mA 4.5 − − 0.4 V IO = 5.2 mA 6.0 − − 0.4 V ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND 6.0 − − ±10.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 40 µA SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) 2003 Jun 30 8 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 Type 74HCT00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Note 1. All typical values are measured at Tamb = 25 °C. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT OTHER VCC (V) Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA 4.5 4.4 4.5 − V IO = −4.0 mA 4.5 3.84 4.32 − V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA 4.5 − 0 0.1 V IO = 4.0 mA 4.5 − 0.15 0.33 V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND; IO = 0 5.5 − − ±5.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 20 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − 150 675 µA Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA 4.5 4.4 − − V IO = −4.0 mA 4.5 3.7 − − V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA 4.5 − − 0.1 V IO = 4.0 mA 4.5 − − 0.4 V ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA IOZ 3-state output OFF current VI = VIH or VIL; VO = VCC or GND; IO = 0 5.5 − − ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 40 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − − 735 µA 2003 Jun 30 9 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 AC CHARACTERISTICS Type 74HC00 GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Note 1. All typical values are measured at Tamb = 25 °C. Type 74HCT00 GND = 0 V; tr = tf = 6 ns; CL = 50 pF Note 1. All typical values are measured at Tamb = 25 °C. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH propagation delay nA, nB to nY see Fig.6 2.0 − 25 115 ns see Fig.6 4.5 − 9 23 ns see Fig.6 6.0 − 7 20 ns tTHL/tTLH output transition time 2.0 − 19 95 ns 4.5 − 7 19 ns 6.0 − 6 16 ns Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA, nB to nY see Fig.6 2.0 − − 135 ns see Fig.6 4.5 − − 27 ns see Fig.6 6.0 − − 23 ns tTHL/tTLH output transition time 2.0 − − 110 ns 4.5 − − 22 ns 6.0 − − 19 ns SYMBOL PARAMETER TEST CONDITIONS MIN. TYP MAX. UNIT WAVEFORMS VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH propagation delay nA, nB to nY see Fig.6 4.5 − 12 24 ns tTHL/tTLH output transition time 4.5 − − 29 ns Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA, nB to nY see Fig.6 4.5 − − 29 ns tTHL/tTLH output transition time 4.5 − − 22 ns 2003 Jun 30 10 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 AC WAVEFORMS handbook, halfpage MNA218 tPHL tTHL tTLH tPLH VM VMnA, nB input nY output GND VI VOH VOL Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays. 74HC00: VM = 50%; VI = GND to VCC. 74HCT00: VM = 1.3 V; VI = GND to 3 V. 2003 Jun 30 11 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 PACKAGE OUTLINES UNIT Amax. 1 2 (1) (1)b1 c D (1)ZE e MHL REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT27-1 99-12-2703-02-13 A min. A max. b max.wMEe1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.2542.54 7.62 8.25 7.80 10.0 8.3 2.24.2 0.51 3.2 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.12 0.010.1 0.3 0.32 0.31 0.39 0.33 0.0870.17 0.02 0.13 050G04 MO-001 SC-501-14 MH c (e )1 ME A L se a tin g pl an e A1 w M b1 e D A2 Z 14 1 8 7 b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 2003 Jun 30 12 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 UNIT Amax. A1 A2 A3 bp c D (1) E(1) (1)e HE L Lp Q Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 1.75 0.250.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 SOT108-1 X w M q AA1 A2 bp D HE Lp Q detail X E Z e c L v M A (A )3 A 7 8 1 14 y 076E06 MS-012 pin 1 index 0.069 0.0100.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.0410.2440.228 0.028 0.024 0.028 0.0120.01 0.25 0.01 0.0040.0390.016 99-12-27 03-02-19 0 2.5 5 mm scale SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 2003 Jun 30 13 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 UNIT A1 A2 A3 bp c D(1) E (1) e HE L Lp Q Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.210.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o0.13 0.1 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. SOT337-1 99-12-2703-02-19 (1) w M bp D HE E Z e c v M A X A y 1 7 14 8 q AA1 A2 Lp Q detail X L (A )3 MO-150 pin 1 index 0 2.5 5 mm scale SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 A max. 2 2003 Jun 30 14 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 UNIT A1 A2 A3 bp c D (1) E (2) (1)e HE L Lp Q Zywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.150.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-2703-02-18 w M bp D Z e 0.25 1 7 14 8 q AA1 A2 Lp Q detail X L (A )3 HE E c v M A X A y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index 2003 Jun 30 15 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 terminal 1 index area 0.51 A1 EhbUNIT ye 0.2 c REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 3.12.9 Dh 1.65 1.35 y1 2.6 2.4 1.15 0.85 e1 20.300.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT762-1 MO-241 - - -- - - 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT762-1 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm A(1) max. A A1 c detail X yy1 Ce L Eh Dh e e1 b 2 6 13 9 8 71 14 X D E C B A 02-10-17 03-01-27 terminal 1 index area AC C Bv M w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1) 2003 Jun 30 16 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 DATA SHEET STATUS Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. LEVEL DATA SHEETSTATUS(1) PRODUCT STATUS(2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. © Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Printed in The Netherlands 613508/03/pp17 Date of release: 2003 Jun 30 Document order number: 9397 750 11258 FEATURES DESCRIPTION QUICK REFERENCE DATA FUNCTION TABLE ORDERING INFORMATION PINNING RECOMMENDED OPERATING CONDITIONS LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS AC WAVEFORMS PACKAGE OUTLINES SOT27-1 SOT108-1 SOT337-1 SOT402-1 SOT762-1 DATA SHEET STATUS DEFINITIONS DISCLAIMERS