一、VCS简介
VCS(Verilog Compiled Simulator)定位于大型、复杂电路的快速仿真,主要用于Verilog 源代码的编译仿真,但也能对VHDL、C/C++源代码进行混合仿真。
VCS支持命令行方式(CLI),为了进行图形界面调试,VCS包含了一个图形仿真器VirSim(Virtual Simulator Environment),下面主要讲述VirSim的使用。
二、VCS的简单CLI命令
在VCS的CLI方式下,输入的所有命令都以vcs开头。
vcs -h 帮助命令,列表显示vcs后可跟的所有命令选项及简单解释;
vcs -RI Run Interactive. Starts VirSim
immediately after compilation ;
vcs -line Enables stepping through the code and source line breakpoints in
VirSim ;
vcs +cli+1|2|3|4 +cli Enable CLI debugging,
1enables you to see the values of nets and registers
and deposit values to registers;
2also enables breakpoints on value changes of nets
and registers ;
3also enables you to force a value on nets ;
4also enables you to force a value on a register ;
vcs -Mupdate Enable incremental compilation and
overwrite the make file ;
vcs –M Enable incremental compilation,but
do not overwrite the makefile ;
vcs –f Specifies a file that contains a list of
pathnames to source files and
compile-time options ;
vcs -i
Specifies a file containing CLI
commands that VCS executes when simulation starts ;
VCS是Synopsys公司的仿真工具.
VCS对verilog模型进行仿真包括两个步骤:
1. 编译verilog文件成为一个可执行的二进制文件命令为:
$> vcs source_files
2. 运行该可执行文件
$> ./simv
类似于NC, 也有单命令行的方式:
$> vcs source_files -R
-R 命令表示, 编译后立即执行.
下面讲述常用的命令选项:
-cm line|cond|fsm|tgl|obc|path 设定coverage的方式
+define+macro=value+ 预编译宏定义
-f filename RTL文件列表
+incdir+directory+ 添加include 文件夹
-I 进入交互界面
-l logfile文件名
-P pli.tab 定义PLI的列表(T ab)文件
+v2k 使用推荐的
标准
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-y 定义verilog的库
-notice 显示详尽的诊断信息
-o 指定输出的可执行文件的名字,缺省是sim.v
zz 51life
Summary of vcs compile options:
-------------------------------
-ASFLAGS "opts" pass 'opts' to the assembler
-B generate long call instructions in native assembly code
(HP only)
-CC "opts" pass 'opts' to C compiler
-CFLAGS "opts" pass 'opts' to C compiler
-LDFLAGS "opts" pass 'opts' to C compiler on load line only
-I enable interactive/postprocessing debugging capabilities
-ID get host identification information
-M enable incremental compilation (see manual)
-Mupdate enable incremental compilation and keep the Makefile up-to-date
-Marchive[=N] create intermediate libs to reduce link line length; N objs per lib
-P plitab compiles user-defined pli definition table 'plitab'
-PP enable optimizer postprocessing capabilities for vcd+
-R after compilation, run simulation executable
-RI after compilation, run simulation under xvcs (Implies -I)
-RIG run simulation under xvcs without compiling (executable
has to exist)
-RPP run xvcs in postprocessing mode (requires file created by vcdpluson)
-V[t] verbose mode; with 't', include time information
-as foo use foo as the assembler
-cc foo use foo as the C compiler
-cpp foo use foo as the C++ compiler
-e specify the name of your main() routine.
(see manual section 7-11 for more details).
-f file reads 'file' for other options
-gen_c generate C code (for HP and Sun, default is -gen_obj) -gen_asm generate native assembly code (HP and Sun only)
-gen_obj generate native object code (HP and Sun only)
-ld foo use foo as the linker. (refer vcs manual for compatibility with -cpp option)
-line enable single-stepping/breakpoints for source level debugging
-lmc-swift include lmc swift interface
-lmc-hm include lmc hardware modeler interface
-vera add VERA 4.5+ libraries
-vera_dbind add VERA 4.5+ libraries for dynamic binding
-location display full pathname to vcs installation for this platform -vhdlobj generate a vhdl obj for simulating in a vhdl design -mixedhdl include MixedHDL-1.0 interface
-mhdl include MixedHDL-2.0 interface and library
-q quiet mode
-platform display name of vcs installation subdirectory for this platform
-syslib 'libs' specify system libraries (placed last on the link line) eg -lm
-o exec name the executable simulation model 'exec' (default is 'simv')
-u treat all non text string characters as uppercase
-v file search for unresolved module references in 'file'
-y libdir search for unresolved module references in directory
'libdir'
+acc enable pli applications to use acc routines (see manual) +ad include anlog simulation interface and library
+adfmi="files" ADFMI support for vcs-ace
+cliedit enable command line edit/recall (see doc/readline.ps)
+cli enable command line interactive debugging (see manual) +cmod Enabling cmodule feature
+cmodext+cmodext Changing cmodule extension to cmodext
+cmodincdir+cmoddir Cmodule Include directory
+cmoddefine+macro define cmodule source 'macro' in the form of
XX=YY
+define+macro define hdl source 'macro' to have value "macro"
+plusarg_save hardwire the plusargs, which follow this flag, into
simv
+plusarg_ignore turn off +plusarg_save
+prof tells vcs to profile the the design and generate vcs.prof
file
+race tells vcs to generate a report of all race conditions during simulation
and write this report in the race.out file
+rad+1 enable level 1 radiant optimizations (See Release Notes) +rad+2 enable level 2 radiant optimizations (See Release Notes) +libext+lext use extension 'lext' when searching library directorys
+librescan search from beginning of library list for all undefined
mods
+incdir+idir for `include files, search directory 'idir'
+nospecify suppress path delays and timing checks
+notimingchecks suppress timing checks
+optconfigfile+foo use 'foo' as the optimization config file (See Release
Notes)
+vcsd enable the VCS Direct sim kernel interface
-cmhelp enable CoverMeter help. CoverMeter should be
installed
and environment variable CM_HOME should be set.
-cm enable VCS to first run cmSource to instrument the
Verilog source files on the command line, and then to
compile the instrumented source files
-cm_all enable VCS to link CoverMeter into the VCS executable in a way that enables line, condition, and FSM coverage
and establishes the direct link. Enabling all types of coverage and the
direct link is the default condition when you include the -cm option so
you can omit this option
-cm_lineonly enable VCS to link CoverMeter into the VCS
executable in a way that only enables line coverage when it
also establishes the direct link. Use this option for faster simulation and when you only need line coverage
Compile-Time Options
********************
-f
Specifies a file that contains a list of pathnames to source files
and compile-time options.
-F
Same as the -f option but allows you to specify a path to the file
and the source files listed in the file do not have to be absolute pathnames.
-h
Displays a succinct description of the most commonly used compile-time and runtime options.
-l
(lower case L) Specifies a log file where VCS records compilation messages and runtime messages if you include the -R, -RI, or
-RIG options.
-line
Enables stepping through the code and source line breakpoints in VirSim. -M
Enables incremental compilation, but do not overwrite the makefile.
-Mupdate
Enable incremental compilation and overwrite the make file.
-notice
Enables verbose diagnostic messages.
-o
Specifies the name of the executable file that is the product of compilation. The default name is simv (simv.exe on Windows).
-ova_cov
Enables functional coverage.
-P
Specifies a PLI table file.
-R
Run the executable file immediately after VCS links together the executable file. You can add any runtime option to the vcs command line.
-s
Stop simulation just as it begins. Use this option with the -R and
+cli options.
-timescale=/
If only some source files contain the `timescale compiler directive
and the ones that don't appear first on the vcs command line, use
this option to specify the time scale for these source files.
-V
Enables the verbose mode.
-v
Specifies a Verilog library file to search for module definitions.
Specifies the standard VERA PLI table file and object library.
-y
Specifies a Verilog library directory to search for module definitions.
+2state
Enables 2 state simulation.
+cli+[=]1|2|3|4
Enable CLI debugging.
1 enables you to see the values of nets and registers and deposit values to registers.
2 also enables breakpoints on value changes of nets and registers.
3 also enables you to force a value on nets.
4 also enables you to force a value on a register.
You can specify a module to enable CLI debugging only for instances of the module.
+define+=
Defines a text macro. Test for this definition in your Verilog
source code using the `ifdef compiler directive.
+incdir+
Specifies the directories that contain the files you specified with
the `include compiler directive. You can specify more that one directory, separating each path name with the + character.
+libext+
Specifies that VCS only search the source files in a Verilog library directory with the specified extension. You can specify more than one extension, separating each extension with the + character.
For example, +libext++.v specifies searches library files with no extension and library files with the .v extension.
Enter this option when you enter the -y option.
+maxdelays
Use maximum value when min:typ:max values are encountered in delay specifications SDF files.
+mindelays
Use minimum value when min:typ:max values are encountered in delay specifications and SDF files.
+notimingcheck
Suppresses timing checks in specify blocks.
+plusarg_ignore
Also enter this option in the file that you specify with the -f option so that VCS does not pass to the simv executable or to VirSim the options that follow in the file. Use this option with the
+plusarg_save option to specify that other options should
not be passed.
Specifies that VCS generate a report, during simulation, of all the
race conditions in the design and write this report in the race.out
file.
+race=all
Analyzes the source code during compilation to look for coding
styles that cause race conditions.
+rad or +rad+2
Performs aggressive optimizations on your design.
+rad+1 or +radlite or +radlight
Performs less aggressive optimizations on your design.
+v2k
Enables the use of new Verilog constricts in the 1364-2001 standard.
Runtime Options
***************
-i
Specifies a file containing CLI commands that VCS executes when simulation starts.
-l
Specifies writing all messages from simulation to the specified
file as well as displaying these messages in the standard output.
This option begins with the letter "l" (lowercase "L") for log file.
-ova_cov
Enables functional coverage reporting.
-s
Stops simulation just as it beings, and enters interactive mode.
Use with the +cli+ option.
-V
Verbose mode. Print VCS version and extended summary information. Prints VCS compile and run-time version numbers, and copyright information, at start of simulation.
-vcd
Sets the output VCD file name to the specified file.
The default filename is verilog.dump.
A $dumpfile system task in the Verilog source code will override
this option.
+maxdelays
Species using the compiled SDF file for maximum delays generated
by the +allmtm compile-time option.
Also specifies using maximum delays for SWIFT VMC or SmartModels or Synopsys hardware models if you also enter the
+override_model_delays runtime option.
+mindelays
Specifies using the compiled SDF file for minimum delays generated
by the +allmtm compile-time option.
Also specifies using minimum delays for SWIFT VMC or SmartModels or Synopsys hardware models if you also enter the
+override_model_delays runtime option.
+notimingcheck
Suppress timing checks.
+override_model_delays
Enables you to use the +mindelays, +typdelays, or +maxdelays runtime options to specify timing for SWIFT SmartModels or Synopsys hardware models.
+sdfverbose
Enables the display of more than ten warning and ten error messages about SDF back annotation.
+vcs+dumpoff++
Turn off value change dumping ($dumpvars system task) at time .
is the high 32 bits of a time value greater than 32 bits.
+vcs+dumpon++
Suppress $dumpvars system task until time .
is the high 32 bits of a time value greater than 32 bits.
+vcs+dumpvarsoff
Suppress $dumpvars system tasks.
+vcs+finish++
Finish simulation at time .
is the high 32 bits of a time value greater than 32 bits.
Options for Using VirSim Interactively or in Post-Processing
************************************************************
+cfgfile+
Specifies using a configuration file that you recorded in a
previous session with VirSim.
+vslogfile[+]
Enables logging of VirSim commands in a VirSim log file. If you do not specify a filename, the log is automatically saved to the working directory as VirSim.log.
Options For Using VirSim
************************
the following are options for using VirSim. You enter them on the
vcs command line and also specify the source files.
Options for Using VirSim interactively with VCS
+++++++++++++++++++++++++++++++++++++++++++++++
-RI
Run Interactive. Starts VirSim immediately after compilation.
-RIG
Run Interactive Debug. Start VirSim using an existing executable
file (such as the simv or simv.exe file). VCS does no compilation.
+sim+
Use with the -RIG option. You need this option to specify the name
of the simv executable file that isn't named simv but has a different name that you specified with the -o compile-time option.
+vslogfilesim[+]
Enables the logging of VCS communication messages in the VirSim log file. If you use both +vslogfile and +vslogfilesim, VirSim commands and VCS messages are saved to the same file.
If you do not specify a filename, the log is automatically saved
to the working directory as VirSim.log.
+vpdfile+
At runtime, defines an alternative name of the VCD+ file that VCS writes instead of the default name vcdplus.vpd.
Options for Using VirSim in Post-Processing
+++++++++++++++++++++++++++++++++++++++++++
-RPP
Run Post-Processing mode. Starts VirSim for post-processing a VCD+ file.
+vcdfile+
Specifies the VCD file you want to use for post-processing.
+vpdfile+[+start++end+]
In post-processing, specifies the VCD+ file you wish to view in VirSim. The optional +start+ and +end+ arguments specify you only want VirSim to display the results
from between these simulation times.
Options for Specifying How VCS Writes the VCD+ File
+++++++++++++++++++++++++++++++++++++++++++++++++++
-PP
Enables system tasks and options for VCD+ files and optimizations
for faster post-processing.
-I
Enables system tasks and options for VCD+ files.
+vpdbufsize+
VCS uses an internal buffer to store value changes before it writes them to the VCD+ file on disk. VCS makes this buffer size either 5 MB or large enough to record 15 value changes for all nets and registers in your design, which ever is larger.
You can use this option to override the buffer size that VCS calculates for the buffer size. You specify a buffer size in megabytes.
+vpddrivers
Tells VCS to record the values of all the drivers of all the nets.
+vpdfilesize+
Specifies the maximum size of the VCD+ file. When VCS reaches this limit, VCS overwrites the oldest simulation history data in the file with the newest.
+vpdignore
Tells VCS to ignore $vcdplus system tasks so VCS does not write a VCD+ file.
+vpdports
Tells VCS to record, in the VCD+ file, the port direction of signals that are ports.
+vpdnocompress
Disables the automatic compressing of the data in VCD+ files.
+vpdupdate
If VCS is writing a VCD+ file during simulation, this option enables you to have VCS halt writing to the VCD+ file while the simulation is running and so that you can view the recorded results in VirSim. This option enables you to use the update feature in VirSim.
+vpdnostrengths
Disables recording strength information in the VCD+ file.
Options For CAlling The vcd2vpd and vpd2vcd Utilities
*****************************************************
-vcd2vpd
Tells VCS to find and run the vcd2vpd utility that converts a VCD file to a VCD+ file. VCS inputs to the utility the specified VCD
file and the utility outputs the specified VCD+ file.
-vpd2vcd
Tells VCS to find and run the vpd2vcd utility that converts a VCD+ file to a VCD file. VCS inputs to the utility the specified VCD+
file and the utility outputs the specified VCD file.
The Virsim debugger and the vpd2vcd and vcd2vpd translator utilities are best invoked via the vcs command line.
Summary of vcs options for the $vcdpluson tasks:
------------------------------------------------
-I enable interactive/postprocessing debugging capabilities
-PP enable optimizer postprocessing capabilities for vcd+
+vcsd enable the VCS DKI (Direct Kernel Interface); +vpdports,
+vpddrivers, output and interactive
simulation currently are not available in +vcsd mode.
Summary of vcs options for the Virsim GUI:
------------------------------------------
-RI after compilation, run simulation under Virsim (implies -I)
-RIG run simulation under Virsim without compiling (executable has to exist)
-RPP run Virsim in postprocessing mode (requires file created by $vcdpluson)
Additional Virsim Verilog and $vcdpluson flags:
-----------------------------------------------
VirSim 4.3.R11 Virtual Simulator Environment
Copyright (C) 1993-2003 by Synopsys, Inc.
Licensed Software. All Rights Reserved.
Usage: vcs [-RI|-RIG|-RPP] [[+vpdfile+]...] [[+vcdfile+]...] [[+cfgfile+ ]...]
[sim-opts] [vpd-opts-to-pli] [other-opts] files
+vpdfile+ Multiple VPD files can be opened using several
+vpdfile+ commands
+vcdfile+ Multiple VCD files can be opened using several
+vcdfile+ commands
+cfgfile+ Multiple (incremental) configuration files can be loaded
sim-opts:
+sim+ Sets simulator path name
+simtype+ Sets simulator type exactly as listed in Simulator
Invocation Dialog
+simargs+ Sets additional simulator arguments. Double quotes
around multiple arguments.
+simargs+"+vpdfile+" Sets name of VPD file to be created by VCD+ PLI vpd-opts-to-pli: Options for VCD+ generation by an interactive
simulation run started by virsim
+vpdports Stores port type information for hierarchy
+vpddrivers Stores data for changes on drivers of resolved nets
+vpdbufsize+<#MB> Changes the default size of the internal VCD+ buffer
+vpdfilesize+<#MB> Sets file size when storing data in wraparound mode
+vpdupdate Enables VPD file locking
+vpdignore Tells simulator to ignore all calls to generate VPD
+vslogfile Enables message logging. Does not log simulation communication messages
+vslogfile+ Enables message logging. Logs messages in filename
+vslogfilesim Enables logging of simulation communication messages
other-opts: Sets regular options to compile verilog code
+v2k Enables supported verilog 2000 additions
files: Verilog source code file(s) list
Summary of vcd2vpd options:
---------------------------
Usage: vcs -vcd2vpd
-b# Buffer size in KB used to store Value Change Data before
writing it to disk.
-f# Maximum output file size in KB. Wrap around occurs if
the specified file size is reached.
-h Translate hierarchy information only.
-m Give tranlsation metrics during translation.
-q Suppress printing of copyright and other informational messages.
+deltacycle Add delta cycle information to each signal value change.
+glitchon Add glitch event detection data.
+nocompress Turn data compression off.
+nocurrentvalue Do not include object's current value at the beginning of each VCB.
+dut+ Modifies the string identifier for the Device-Under-Test
half of the split signal. Default is "DUT".
+tf+ Modifies the string identifier for the Test-Fixture
half of the split signal. Default is "TF".
+indexlast Appends the bit index of a vector bit as the last
element of the name.
Summary of vpd2vcd options:
---------------------------
Usage: vcs -vpd2vcd []
Summary of vpd2vcd command line options
-h Translate hierarchy information only.
-q Suppress printing of copyright and other informational messages.
-s Allow sign extension for vectors. Reduces size of .
-x Expand vector variables to full length when displaying
$dumpoff value blocks.
+zerodelayglitchfilter Zero delay glitch filtering for multiple value changes within the same time unit.
+morevhdl Translates the vhdl types that are not directly mappable to
verilog types in addition to the ones that are mappable.
+start+ Translate value changes starting after start time
+end+ Translate value changes ending before end time
(Note) If both start and end values are input, value changes
occuring between start and end time are translated.
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