VbyOne_Spec_V1.4

V-by-One® HS Standard_Ver.1.4 1 Copyright(C)2011 THine Electronics, Inc. R V-by-One® HS Standard Version 1.4 December 15, 2011 Abridged Edition V-by-One® HS Standard_Ver.1.4 2 Copyright(C)2011 THine Electronics, Inc. R Table of Contents Table of Contents................................................................................................................................................. 2 1. Introduction ..................................................................................................................................................... 4 1.1. Objectives................................................................................................................................................ 4 1.2. Technical Overview................................................................................................................................. 4 1.2.1. Transmitter....................................................................................................................................... 5 1.2.2. Receiver........................................................................................................................................... 5 1.2.3. Data Lane ........................................................................................................................................ 5 1.2.4. HTPDN signal ................................................................................................................................. 7 1.2.5. LOCKN signal................................................................................................................................. 7 2. Link Specification ........................................................................................................................................... 8 2.1. Functional Specification.......................................................................................................................... 9 2.1.1. Packer and Unpacker....................................................................................................................... 9 2.1.2. Scrambler and Descrambler........................................................................................................... 14 2.1.3. Encoder and Decoder .................................................................................................................... 17 2.1.4. Serializer and Deserializer............................................................................................................. 18 2.1.5. Link status monitor........................................................................................................................ 19 2.2. Operating Specification ......................................................................................................................... 20 2.2.1. Transmitter State Diagram............................................................................................................. 20 2.2.2. Receiver State Diagram................................................................................................................. 21 2.2.3. Link Start up flow.......................................................................................................................... 22 2.2.4. Link Disable flow.......................................................................................................................... 23 2.2.5. Trainings........................................................................................................................................ 24 3. Electrical Specification.................................................................................................................................. 28 3.1. Overview ............................................................................................................................................... 28 3.2. Transmitter Electrical Specifications..................................................................................................... 29 3.3. Receiver Electrical Specifications ......................................................................................................... 33 3.4. Eye Diagram Measurement Setting....................................................................................................... 35 3.5. Power on/off and Power down specification ......................................................................................... 35 3.6. Optional functions ................................................................................................................................. 35 3.6.1. Pre-emphasis ................................................................................................................................. 35 3.6.2. Equalizer........................................................................................................................................ 35 4. Guideline for interoperability ........................................................................................................................ 36 4.1. Byte length and Color mapping............................................................................................................. 36 Abridged Edition V-by-One® HS Standard_Ver.1.4 3 Copyright(C)2011 THine Electronics, Inc. R 4.2. Multiple Data Lane combination........................................................................................................... 38 4.2.1. Allocation of pixel to Data Lane ................................................................................................... 38 4.2.2. Inter-lane skewing ......................................................................................................................... 40 4.2.3. RGB+CMY color mode................................................................................................................. 40 4.3. 3D frame identification.......................................................................................................................... 41 4.3.1. 3D flag on blanking period............................................................................................................ 41 4.3.2. 3D flag on DE active period .......................................................................................................... 42 4.4. Countermeasure against frequency change ........................................................................................... 43 5. Connector and Cable ..................................................................................................................................... 44 5.1. Interoperability order of priority............................................................................................................ 44 5.2. Pin assignments ..................................................................................................................................... 49 5.2.1. Normal ground format ................................................................................................................... 49 5.2.2. Reduced ground format ................................................................................................................. 50 5.3. Connector Characteristics...................................................................................................................... 53 5.3.1. Electrical........................................................................................................................................ 53 5.3.2. Recommended Receptacle Interface Dimensions.......................................................................... 53 5.4. PCB Layout Considerations .................................................................................................................. 54 6. Glossary......................................................................................................................................................... 55 7. Revision history............................................................................................................................................. 56 8. Notice and Requires ...................................................................................................................................... 57 Abridged Edition V-by-One® HS Standard_Ver.1.4 4 Copyright(C)2011 THine Electronics, Inc. R 1. Introduction 1.1. Objectives „ V-by-One® HS targets a high speed data transmission of video signals based on internal connection of the equipment. „ V-by-One® HS pursues easier usage and lower power consumption compared with the current internal connection. „ V-by-One® HS supports up to 4Gbps data rate (effective data rate 3.2Gbps). „ V-by-One® HS supports scrambling and Clock Data Recovery (CDR) to reduce EMI. „ V-by-One® HS supports CDR to solve the skew problem between clock and data at conventional transfer system. 1.2. Technical Overview With V-by-One® HS proprietary encoding scheme and CDR architecture, V-by-One® HS technology enables transmission up to 40bit video data, up to 24bit CTL data, HSYNC, VSYNC and Data Enable (DE) by some differential pair cables with minimal external components. As shown in Figure 1, V-by-One® HS Link includes Data Lanes, Hot Plug Detect signal (HTPDN), and CDR Lock signal (LOCKN). Number of Data Lanes is decided with the pixel rate and color depth (see Table 1). HTPDN connection between transmitter and receiver can be omitted as an application option. As optional functions, it is possible to implement transmitter pre-emphasis and receiver equalizer. Figure 1 V-by-One® HS Link system Diagram TX0n RX0n TX0p RX0p TX1n RX1n TX1p RX1p HTPDN HTPDN LOCKN LOCKN 10kΩ V-by-One® HS Transmitter Indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω V-by-One® HS Receiver ... TXNn RXNn TXNp RXNp Pixel Data Control Data Pixel Data Control Data VDL Abridged Edition V-by-One® HS Standard_Ver.1.4 5 Copyright(C)2011 THine Electronics, Inc. R 1.2.1. Transmitter V-by-One® HS Transmitter consists of packer, scrambler, encoder, serializer, and transmitter link monitor (Figure 3). Transmitter link monitor constantly monitor LOCKN and HTPDN signals. If the LOCKN signal is High, Transmitter executes the CDR training. Transmitter sends the CDR training pattern on the CDR training mode. When CDR locked, Transmitter shifts from CDR training mode to the normal mode, and then it starts to transmit input data from user logic. 1.2.2. Receiver V-by-One® HS Receiver consists of unpacker, de-scrambler, decoder, de-serializer and receiver link monitor. The Receiver synchronizes the pixel clock while referring to the CDR training pattern on the CDR training mode. After shifting from the CDR training mode to the normal mode, the Receiver aligns byte and bit position using ALN training pattern. About ALN training, please refer to 2.2.5.2 in page 25). 1.2.3. Data Lane Data Lane is AC-coupled differential pairs with termination. Transmission rate is able to be set up to 4Gbps depend on video pixel clock rate and bit depth. 1.2.3.1. Recommended data lane Table 1 Video data format vs. No of lane example Resolution Refresh rate (Pixel clock) color depth No of data lane* 60Hz(74.25MHz) 18/24/30/36 bit 1 120Hz(148.5MHz) 18/24/30/36 bit 2 HD ex. 1280 x 720p 240Hz(297MHz) 18/24/30/36 bit 4 60Hz(148.5MHz) 18/24/30/36 bit 2 120Hz(297MHz) 18/24/30/36 bit 4 240Hz(594MHz) 18/24/30/36 bit 8 Full HD ex. 1920 x 1080p 480Hz(1188MHz) 18/24/30/36 bit 16 60Hz(185MHz) 18/24/30 bit 2 120Hz(370MHz) 18/24/30 bit 4 Cinema Full HD ex. 2560 x 1080p 240Hz(740MHz) 18/24/30 bit 8 60Hz(594MHz) 18/24/30/36 bit 8 120Hz(1188MHz) 18/24/30/36 bit 16 4K x 2K ex. 3840 x 2160p 240Hz(2376MHz) 18/24/30/36 bit 32 * Another lane number could be chosen; however, for the interoperability, those are STRONGLY recommended. Abridged Edition V-by-One® HS Standard_Ver.1.4 6 Copyright(C)2011 THine Electronics, Inc. R 1.2.3.2. Data lane consideration This chapter is informative only. It shows the procedure to select the minimum and maximum number of lanes necessary for the target application. As a 1st step, [byte mode] (please refer to 2.1.1.4) is chosen from 3, 4, or 5 depending upon color depth. Literally 3, 4, or 5 byte mode convey nominal 3, 4, or 5byte data. For example, 10bit per color RGB image requires 30 bit data per pixel; therefore, 4 byte mode which conveys 4 byte (32 bit) is enough to carry the data. As a 2nd step, total bit rate which is physically transmitted on V-by-One® HS line should be estimated. Because V-by-One® HS uses 8b10b encoding scheme, encoded data amount which is physically transmitted is 10bit per nominal decoded 8bit (1 byte) of original data. Multiplying [pixel clock] of the target application by encoded data amount per pixel results into [encoded total bit-rate] of V-by-One® HS transmission. [encoded bit-rate per lane] can be calculated as [total bit rate] over [number of lanes] [number of lanes] should be chosen properly so that [encoded bit-rate per lane] is above 600Mbps and below 4Gbps. [number of lanes] should be selected appropriate to signal handling in applications. For example, in case of video signal transmission, [number of lanes] is recommended to be divisor of Hactive, Hblank, and Htotal pixel number like 1, 2, 4, 8, etc. in order to help signal processing. Abridged Edition V-by-One® HS Standard_Ver.1.4 7 Copyright(C)2011 THine Electronics, Inc. R 1.2.4. HTPDN signal HTPDN indicates connecting condition between the Transmitter and the Receiver. HTPDN of the transmitter side is High when the Receiver is not active or not connected. Then Transmitter can enter into the power down mode. HTPDN is set to Low by the Receiver when Receiver is active and connects to the Transmitter, and then Transmitter must start up and transmit CDR training pattern for link training. HTPDN is open drain output at the receiver side. Pull-up resistor is needed at the transmitter side. HTPDN connection between the Transmitter and the Receiver can be omitted as an application option. In this case, HTPDN at the Transmitter side should always be taken as Low. Figure 2 V-by-One® HS Link system without HTPDN connection schematic Diagram 1.2.5. LOCKN signal LOCKN indicates whether the CDR PLL is in the lock state or not. LOCKN at the Transmitter input is set to High by pull-up resistor when Receiver is not active or at the CDR PLL training state. LOCKN is set to Low by the Receiver when CDR lock is done. Then the CDR training mode finishes and Transmitter shifts to the normal mode. LOCKN is open drain output at the receiver side. Pull-up resistor is needed at the transmitter side. When HTPDN is included in an application, the LOCKN signal should only be considered when the HTPDN is pulled low by the Receiver. TX0n RX0n TX0p RX0p TX1n RX1n TX1p RX1p HTPDN HTPDN LOCKN LOCKN 10kΩ V-by-One® HS Transmitter Indicates microstrip lines or cables with their differential characteristic impedance being 100 Ω V-by-One® HS Receiver ... TXNn RXNn TXNp RXNp Pixel Data Control Data Pixel Data Control Data VDL GND Abridged Edition V-by-One® HS Standard_Ver.1.4 36 Copyright(C)2011 THine Electronics, Inc. R 4. Guideline for interoperability In this chapter, guideline for interoperability is described. 4.1. Byte length and Color mapping The V-by-One® HS can be used to various types of color video format allocating D[39:0] to pixel data in packer and unpacker mapping. The color data mapping should refer to Table 11 and Table 12 Table 11 RGB/YCbCr444/RGBW/RGBY color data mapping 36bpp RGB /YCbCr444 30bpp RGB /YCbCr444 24bpp RGB /YCbCr444 18bpp RGB /YCbCr444 40bpp RGBW / RGBY 32bpp RGBW / RGBY D[0] R/Cr[4] R/Cr[2] R/Cr[0] - R[2] R[0] D[1] R/Cr[5] R/Cr[3] R/Cr[1] - R[3] R[1] D[2] R/Cr[6] R/Cr[4] R/Cr[2] R/Cr[0] R[4] R[2] D[3] R/Cr[7] R/Cr[5] R/Cr[3] R/Cr[1] R[5] R[3] D[4] R/Cr[8] R/Cr[6] R/Cr[4] R/Cr[2] R[6] R[4] D[5] R/Cr[9] R/Cr[7] R/Cr[5] R/Cr[3] R[7] R[5] D[6] R/Cr[10] R/Cr[8] R/Cr[6] R/Cr[4] R[8] R[6] D[7] R/Cr[11] R/Cr[9] R/Cr[7] R/Cr[5] R[9] R[7] D[8] G/Y[4] G/Y[2] G/Y[0] - G[2] G[0] D[9] G/Y[5] G/Y[3] G/Y[1] - G[3] G[1] D[10] G/Y[6] G/Y[4] G/Y[2] G/Y[0] G[4] G[2] D[11] G/Y[7] G/Y[5] G/Y[3] G/Y[1] G[5] G[3] D[12] G/Y[8] G/Y[6] G/Y[4] G/Y[2] G[6] G[4] D[13] G/Y[9] G/Y[7] G/Y[5] G/Y[3] G[7] G[5] D[14] G/Y[10] G/Y[8] G/Y[6] G/Y[4] G[8] G[6] D[15] G/Y[11] G/Y[9] G/Y[7] G/Y[5] G[9] G[7] D[16] B/Cb[4] B/Cb[2] B/Cb[0] - B[2] B[0] D[17] B/Cb[5] B/Cb[3] B/Cb[1] - B[3] B[1] D[18] B/Cb[6] B/Cb[4] B/Cb[2] B/Cb[0] B[4] B[2] D[19] B/Cb[7] B/Cb[5] B/Cb[3] B/Cb[1] B[5] B[3] D[20] B/Cb[8] B/Cb[6] B/Cb[4] B/Cb[2] B[6] B[4] D[21] B/Cb[9] B/Cb[7] B/Cb[5] B/Cb[3] B[7] B[5] D[22] B/Cb[10] B/Cb[8] B/Cb[6] B/Cb[4] B[8] B[6] D[23] B/Cb[11] B/Cb[9] B/Cb[7] B/Cb[5] B[9] B[7] D[24] (3DLR*) (3DLR*) - - R[0] - D[25] (3DEN*) (3DEN*) - - R[1] - D[26] B/Cb[2] B/Cb[0] - - G[0] - D[27] B/Cb[3] B/Cb[1] - - G[1] - D[28] G/Y[2] G/Y[0] - - B[0] - D[29] G/Y[3] G/Y[1] - - B[1] - D[30] R/Cr[2] R/Cr[0] - - W/Y[0] - D[31] R/Cr[3] R/Cr[1] - - W/Y[1] - D[32] - - - - W/Y[2] W/Y[0] D[33] - - - - W/Y[3] W/Y[1] D[34] B/Cb[0] - - - W/Y[4] W/Y[2] D[35] B/Cb[1] - - - W/Y[5] W/Y[3] D[36] G/Y[0] - - - W/Y[6] W/Y[4] D[37] G/Y[1] - - - W/Y[7] W/Y[5] D[38] R/Cr[0] - - - W/Y[8] W/Y[6] D[39] R/Cr[1] - - - W/Y[9] W/Y[7] Byte2 Byte3 Byte4 Packer input & Unpacker output Byte0 Byte1 Mode 3b yt e m od e 4b yt e m od e 5b yt e m od e * Implementation specific Abridged Edition V-by-One® HS Standard_Ver.1.4 37 Copyright(C)2011 THine Electronics, Inc. R Table 12 YCbCr422 color data mapping 32bpp YCbCr422 24bpp YCbCr422 20bpp YCbCr422 16bpp YCbCr422 D[0] Cb/Cr[8] Cb/Cr[4] Cb/Cr[2] Cb/Cr[0] D[1] Cb/Cr[9] Cb/Cr[5] Cb/Cr[3] Cb/Cr[1] D[2] Cb/Cr[10] Cb/Cr[6] Cb/Cr[4] Cb/Cr[2] D[3] Cb/Cr[11] Cb/Cr[7] Cb/Cr[5] Cb/Cr[3] D[4] Cb/Cr[12] Cb/Cr[8] Cb/Cr[6] Cb/Cr[4] D[5] Cb/Cr[13] Cb/Cr[9] Cb/Cr[7] Cb/Cr[5] D[6] Cb/Cr[14] Cb/Cr[10] Cb/Cr[8] Cb/Cr[6] D[7] Cb/Cr[15] Cb/Cr[11] Cb/Cr[9] Cb/Cr[7] D[8] Y[8] Y[4] Y[2] Y[0] D[9] Y[9] Y[5] Y[3] Y[1] D[10] Y[10] Y[6] Y[4] Y[2] D[11] Y[11] Y[7] Y[5] Y[3] D[12] Y[12] Y[8] Y[6] Y[4] D[13] Y[13] Y[9] Y[7] Y[5] D[14] Y[14] Y[10] Y[8] Y[6] D[15] Y[15] Y[11] Y[9] Y[7] D[16] - - - - D[17] - - - - D[18] - - - - D[19] - - - - D[20] - - - - D[21] - - - - D[22] - - - - D[23] - - - - D[24] Y[2] - - - D[25] Y[3] - - - D[26] Cb/Cr[2] - - - D[27] Cb/Cr[3] - - - D[28] Y[6] Y[2] Y[0] - D[29] Y[7] Y[3] Y[1] - D[30] Cb/Cr[6] Cb/Cr[2] Cb/Cr[0] - D[31] Cb/Cr[7] Cb/Cr[3] Cb/Cr[1] - D[32] Y[0] - - - D[33] Y[1] - - - D[34] Cb/Cr[0] - - - D[35] Cb/Cr[1] - - - D[36] Y[4] Y[0] - - D[37] Y[5] Y[1] - - D[38] Cb/Cr[4] Cb/Cr[0] - - D[39] Cb/Cr[5] Cb/Cr[1] - - Mode 3b yt e m od e 4b yt e m od e 5b yt e m od e Byte2 Byte3 Byte4 Packer input & Unpacker output Byte0 Byte1 Abridged Edition V-by-One® HS Standard_Ver.1.4 38 Copyright(C)2011 THine Electronics, Inc. R 4.2. Multiple Data Lane combination 4.2.1. Allocation of pixel to Data Lane Depend on the data rate and pixel color depth, it is permitted to increase the Data Lanes. About the multiple Data Lanes combination, refers to Figure 27 as first recommendation. For multiple device tra